Fabrication of integrated circuits (IC) in the semiconductor industry typically employs a series of process steps to pattern features to form ICs on silicon substrates. The iterative patterning process may introduce misalignment errors between the pattern levels and may not form the patterned features of the IC to achieve their intended purpose. As IC geometry sizes have decreased over time, the impact of pattern misalignment on device yield and performance has increased. Accordingly, any techniques to reduce pattern misalignment would be advantageous to IC manufacturers.
The “background” description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as conventional art at the time of filing, are neither expressly nor impliedly admitted as conventional art against the present disclosure.